The present invention relates to a printed circuit board test device with a test pin adapter and to a method for adjusting or positioning the latter. This technology is used to connect the standard basic contact grid of an electronic test apparatus for testing single layer or multi-layer board-type interconnection substrates, such as printed circuit boards, ceramic substrates and the like, to the contact points of the substrate, such as a printed circuit board, to be tested. The contact points of the substrate are in the form of very small and very densely arranged metal contact areas or pads on one or both surfaces of the test specimen for SMD components (i.e. surface mounted components) and/or contact holes (plated-through holes) for "wired" components. The printed circuit boards generally are not yet loaded with such active electric/electronic components. It must be pointed out in this connection that the adapters currently preferred are so-called test pin adapters having therein test pins. Such adapters are used in printed circuit board test devices both for single-sided and for double-sided testing of printed circuit boards. However, other types of "contact elements" are also conceivable, such as so-called "vertical conductor rubber plates", i.e. for example rubber mats with contact wires finely distributed therein and disposed at right angles to the surface, or similar elastic mats which become electrically active upon application of local pressure, such are known in the prior art.
With regard to the testing of unloaded printed circuit boards, the limit of testability thereof was determined in the past mainly by the configuration possibility of the contact test pins in the adapter and by the contact density of the bonding pad (basic grid) of the printed circuit board test device. In keeping with the ever increasing miniaturization of electronic components, there has however occurred every year a further reduction in size of the electric interconnections and contact points and their density on the printed circuit boards to be tested. At the same time, the size of panels has had to be increased for utility-based production to relatively large standard formats, i.e. the standard formats contain a number of identical printed circuit boards or printed circuits, in order thereby to optimize the economic return on the manufacture of the latter.
There therefore arises on an ever increasing scale the problem that the test pins in a supporting element of the adapter cannot be positioned sufficiently accurately in relation to the connecting structures (connecting areas, pads, holes) of the printed circuit board. This gives rise in many cases to defective and/or wrong contact between the contact elements and the connecting structures. These defective contacts make a reliable electrical test of the printed circuit boards extremely difficult or even impossible.
The causes of this problem lie (albeit on a reduced scale) in the adapter and above all in the test specimen or printed circuit board itself. The influence of the adapter on the deviation of the contact points from a target value results both from tolerances during the manufacture of the various components of the adapter and from the requisite clearance between, e.g., the test pins and guides provided for the latter, e.g. a number of drilled plexiglass plates as supporting elements of the adapter. This is exemplified in the following table.
Accuracies of typical test adapters (excluding the influence of temperature during testing) Deviation of the position of .+-.20 .mu.m/.+-.0.8 mil a tip of a contact ele- ment relative to the cen- ter of guide element Overall clearance between .+-.25 .mu.m/.+-.1.0 mil guide element and guide hole Positional tolerance of guide hole .+-.05 .mu.m/.+-.2.0 mil Total overall deviation .+-.50 .mu.m/.+-.2.0 mil
Herein, the term "mil" means a thousandth of an inch. This unit of length has acquired general acceptance in the printed circuit board industry and amounts to 0.0254 mm.
The influence of temperature during the manufacture and use of the adapter can be limited relatively easily by air conditioning. Such influence can therefore be excluded from further consideration.
Far more difficult to control are differences in the geometric structures on the test specimen, i.e. on the printed circuit board to be tested. These differences can be divided into relative positional displacements of an entire image, which can be attributed to recording errors during an exposure process, and to distortions within the image, which can arise through irreversible thermal processes of the test specimen or of a film used for exposure of the printed circuit. By virtue of the sequence of production processes (drilling, exposure, hot tinning, etc.), there are at least four mutually independent sources of error affecting the exact position of conductors and points of connection on the printed circuit board. Thus, the holes in the printed circuit board, the surface structure of the underside of the board, the surface structure of the top side of the board, and the outer contour of the board are four mutually independent overall structural factors. Each of these overall structures of factors possesses its own peculiar distortion/deformation properties affecting the overall geometry of the object, i.e. the board. The orientation of the overall structures to one another can be relatively described or defined by displacement/distortion in X- and Y-directions and by rotation. For an individual printed circuit board in a panel, the distortions can be represented with sufficient accuracy as pure displacements and rotations.
Typically, a "mixed technology" is employed in printed circuit boards. In the latter, both wired components for connection to contact holes and surface-mountable (SMD) components for connection to contact areas or pads are provided on a printed circuit board. The need for this mixed technology is due to the fact that a number of electronic components such as, e.g., processors in high-pole PGAs (pin grid arrays) are not obtainable in surface-mounted form. Economic considerations or other technical factors also lead to use of this mixed technology. Printed circuit boards manufactured for purely surface mounting can be aligned by means of conical reference pins for which the optimum position has been determined manually or optically. This type of alignment, however, does not work for a large proportion of printed circuit boards with the above-mentioned mixed technology, because the large number of conical test pins/contact elements provided for the contacting of contact holes, when they are pressed against the test specimen, unintentionally displace the test specimen into a false position, and hence cancel out the adjusting effect of the reference pins.
EP-A-0 508 561 Al shows an apparatus for electronically testing printed circuit boards including a plurality of generally parallel test pins, each of which has a section of reduced diameter along its length intermediate the ends thereof, with a plate having a plurality of drilled holes in which the test pins are mounted with the reduced diameter portions being located in the holes. The plate is adapted to interfere with shoulders at the ends of the sections of reduced diameter to retain the test pins in the testing apparatus. Any displacement of the test pins relative to each other (if any) takes place only in the axial direction thereof. There is no movement whatsoever of any of the test pins relative to each other in a direction parallel with the printed circuit board, let alone for the purpose of compensating for any production errors in the exact location of any of the contact areas on the printed circuit boards to be tested.
U.S. Pat. No. 5,225,777 discloses a high density test probe assembly and method of fabrication thereof. The probe assembly has a multitude of wire-like probe elements whose exposed tips are spaced on X and Y centers to match the centers of closely spaced surface pads of a VLSI circuit. Interconnections to and from the probe elements (for connection to external test equipment) are provided by a multi-layer arrangement of insulating and conducting layers within the body of the probe assembly. The tips of the probe elements are canted relative to vertical so that when the probe assembly is pushed down into mating position onto a VLSI circuit, the probe elements uniformly deflect laterally in one direction only and give a "wiping" action on contact surface pads of the VLSI circuit together with a desired normal contact force. This prior art reference does not mention the problem of laterally offset contact areas or pads on the object to be tested due to unavoidable production tolerances.